Salary: £100,000 - 100,000 per year Requirements: We require a strong mathematical background with a 1st or 2.1 degree in Mathematics, Physics, Electronics, or a similar subject from a well-respected university. We require strong supporting A-level or equivalent grades. We require expertise in front-end RTL design and verification. We require experience with RTL simulation and synthesis tools. We require proficiency in SystemVerilog, or Verilog/VHDL. We require strong communication skills and the ability to interact with internal and external stakeholders. We require coding skills, ideally in C++ or similar languages. We require an understanding of software engineering best practice. We require the ability to collaborate effectively with peers and stakeholders. We require confidence in running projects and working with a high degree of autonomy. Responsibilities: We lead the creation and verification of reusable RTL components. We design and verify a broad range of RTL components that will form the building blocks of advanced devices. We become the go-to person for optimal design verification using simulation and formal techniques. We collaborate with peers and stakeholders across the business. We run projects and contribute our own areas of expertise to the team. We work closely with a capable engineering team in a friendly, welcoming culture. We apply our front-end design and verification expertise to solve interesting design challenges. Technologies: Architect SystemVerilog Verilog VHDL Hardware More: We are a highly regarded employer known for innovative technology and a friendly, informal culture. This senior RTL Design Architect role is based in our modern Cambridge offices and offers a highly competitive salary of up to £120k depending on experience, plus an excellent benefits package including a performance-related bonus. You will join a well-established development team working with exceptionally bright and capable engineers, enjoying a high degree of autonomy and the chance to take ownership of challenging, high-impact RTL design and verification work. last updated 21 week of 2026