RTL Micro-Architecture Design Engineer DRAM Controller - Market Drayton, UK
Client:
SAMSUNG
Location:
Market Drayton, United Kingdom
Job Category:
Other
EU work permit required:
Yes
Job Reference:
ea00998a19b0
Job Views:
12
Posted:
18.07.2025
Expiry Date:
01.09.2025
Job Description:
Description
Designing and developing CXL and DRAM controller (DDR4/5) based intellectual property.
Collaborate with other architects within the IP level to define micro-architecture.
Deliver high-quality micro-architectural documentation.
Produce RTL code on schedule, meeting PPA goals, using Verilog and/or SystemVerilog.
Responsible for logic design, RTL coding, integration, and timing closure of blocks.
Work with verification team to ensure implementation aligns with architectural intent.
Perform quality checks such as Lint, CDC, and constraint development.
Debug designs in simulation environments.
Deep understanding of digital design fundamentals.
Preferred Skills:
* Strong Verilog/SystemVerilog RTL coding skills.
* Experience with DRAM Memory Controller design.
* Knowledge of DDR4/5 memory standards.
* Experience with interfaces/protocols like AHB/AXI, SPI, UART, etc.
* Experience with Xilinx/Intel FPGA tools.
* Knowledge of PCIe/PIPE.
* Experience with projects involving Microblaze, ARM cores, etc.
* Knowledge of CXL Protocol is a plus.
Skills and Qualifications:
* Master’s or Bachelor’s degree in Electronics or Electrical Engineering.
* 5 to 14 years of relevant experience in RTL design, synthesis, and timing closure.
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