Job Description
Job Title: Senior RFIC (Radio Frequency Integrated Circuit) Design Engineer
Location: Farnborough, UK
Job Type: Full-time contract, 29th January 2027
Work Model: onsite
Summary:
The senior engineer will take on the design of multiple RF blocks including RF buffers and LO blocks and also contribute to the verification of designs by performing full Rx chain verification simulations, reporting compliance to spec and validating device register controls for test. The tasks will include:
• Review of block specifications.
• Schematic design, simulation and reporting compliance to specifications.
• Overseeing a layout engineer to complete the layout.
• Post-layout parasitic simulation and necessary adjustments.
• Documentation of usage and any calibrations etc.
• Liaising with the relevant technical lead to integrate the designs.
• Presentation of design for block-level reviews.
• Completing top level verification simulations
o Reporting compliance to spec
o Validating device register control settings for test
Key Responsibilities:
• Acts as a key contributor in a complex environment.
• Responsible for the delivering the fully verified blocks.
• Solves complex problems in a tightly constrained environment.
• Fully competent in Analogue design for complex sub-cells and small subsystems.
• Keeps abreast of new developments and is technical expert in the design of analogue sub-cells.
• Ensures quality of the solution; works with macro lead to ensure timely delivery of subsystems.
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field
Minimum Experience:
Candidate should have:
• 5+ year of RFIC work experience.
• Design experience of Key RF IPs like LO buffers, RF test circuitry.
• Experience of verification simulations of complete transceiver chains RF -> Analogue
• Good understanding of RFIC design.
• Experience with either Cadence or Mentor RF/Analogue IC design tools.
• Ability to coordinate with different team members and define the requirements.
• Experience in a relatively low geometry node (≤40nm) CMOS process.
Preferred Experience:
• Fully competent in RFIC design and verification techniques.
• Fully competent in the use of Cadence RF/analogue design and verification tools.
• Recent LO or RF buffer or RF test design experience.
• Good team player.
• Good interpersonal and communication skills.