* Collaborate with architects, hardware, and verification engineers to refine and implement new DSP features for cutting-edge and next-generation SerDes transceivers with a focus on low power
* Implement DSP algorithms for equalization, filtering and sequence detection
* RTL development and using front-end ASIC tools (lint, synthesis, STA) to ensure the highest quality code
* Develop comprehensive documentation detailing DSP algorithm interactions with SerDes hardware and software components, #LI-PL1
#LI-Hybrid #Edinburgh Benefits offered are described:. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available This posting is for an existing vacancy.
* Proven experience in DSP algorithm development and implementation for SerDes, wireless communications or high-speed serial interfaces (Ethernet, PCIe, etc.)
* Familiarity with equalization techniques such as FFE, CTLE, DFE or MLSE and their implementation
* Strong background and experience in digital design techniques including clock domain crossing, RTL (preferably SystemVerilog), and ASIC front-end design tools and flows
* Understanding of power analysis and techniques for optimization of digital designs for low power
* Familiarity with simulation and modeling of DSP blocks in SerDes
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