Job Title: CPU Research Engineer
Location: Cambridge, UK (Full Time On-Site)
Type: Fixed Term Contract
Duration: 12 Months (Highly Likely to Extend)
Key Responsibilities:
Research and develop next-generation data prefetching techniques including ML-based predictors and irregular access pattern prediction.
Design advanced speculative execution mechanisms and thread-level speculation (TLS).
Research branch prediction innovations including neural branch predictors, path-based prediction, slice-based prediction, and conditional control flow slice techniques.
Design ISA extensions and microarchitectural support for compiler-directed optimizations including software pipelining and instruction scheduling hints.
Propose microarchitectural support for JIT compilation, dynamic optimization, and adaptive execution.
Design simulation and prototyping frameworks integrating compiler toolchains with architectural models for microarchitectural evaluation.
Participate in joint research projects with top tier UK universities, compiler teams, and OS kernel developers on future processor architectures.
Requirements:
Master/PhD degree in Computer Science/Engineering/Physics etc.
Strong knowledge of advanced computer architectures, superscalar processor design, and compiler design principles.
Deep understanding of speculative execution, branch prediction, and out-of-order execution.
Strong programming skills in C, C++, Python, assembly languages (Arm64 assembly or RISC-V assembly), and scripting languages.
Experience with cycle-accurate microarchitecture simulation and performance modelling.
Desirables:
Experience with gem5, Sniper, ChampSim, or other cycle-accurate detailed microarchitecture simulators.
Experience with LLVM backend development or custom ISA extension implementation.
Strong knowledge of profile-guided optimization (PGO) and feedback-directed optimization.
Experience with compiler development (LLVM, GCC) or compiler optimization techniques.
Experience with OS kernel development and understanding of scheduler and memory manager internals.
Knowledge of binary translation, dynamic binary instrumentation, or JIT compilation techniques.
Understanding of hardware-enforced security mechanisms (CFI, PAC, BTI, MTE on Arm).
Experience with co-simulation frameworks integrating ISA simulators with compiler toolchains.
Familiarity with emerging technologies: processing-in-memory (PIM), near-data processing, chiplet architectures.
If this sounds of interest, please apply here or reach out to daniel@microtech-global.com