Overview
We have an exciting opportunity for a Layout Engineer to join the excellent IC Engineering team at Pragmatic Semiconductor. Based in Cambridge and reporting to the Senior Manager - IC Layout, the successful candidate will collaborate with multiple teams to produce high quality layouts and significantly support the progress of our Product roadmap.
You will be part of a supportive Layout team and wider IC Engineering function, working on all aspects of Layout, which includes supporting both present and future generation technologies by providing top level chip designs.
We are looking for candidates ideally with broad experience of the full Layout process flow, and a solid understanding of parasitics (using methodologies such as routing, matching and shielding) and verification (using LVS, DRC etc).
We are offering a highly attractive benefits package for this position, including visa sponsorship/relocation support to the UK (Cambridge).
Key tasks
* Work in partnership with analogue designers to deliver high quality layouts to support Pragmatic’s product roadmap
* Complete Analog-on-Top Chip level layout floor planning, integration and tape-out activities
* Perform detailed transistor level layout designs for Custom Analog Block-IP, such as PLLs and ADCs
* Develop Logic libraries/IO and memory library from scratch based on latest Pragmatic technology and process updates
* Perform block and chip level verifications such as LVS / DRC / Extraction using industry standard verification tools
* Active participation in the Design Review process, documentation and ownership of the designs
* Develop a strong understanding of the PDK and design requirements in order to create high quality layouts
* Develop DTCO test chips on new technologies and process
* Work with our process teams to develop and guide DFM rules
* Support R&D team on the next-generation technology
Qualifications and training
The successful candidate will ideally be educated to degree / postgraduate degree level, or will possess equivalent experience.
Skills and experience
ESSENTIAL
* Demonstrable experience of transistor level designs from scratch
* Excellent understanding of layout challenges such as parasitics, matching, shielding etc.
* Strong knowledge of library development (IO/Logic/Memory) from scratch
* Good understanding of custom layouts like PLLs and ADCs
* Well versed in using industry standard design tools (such as Cadence Virtuoso) and verification tools
* Good understanding of DRC, LVS verification and industrial standard tools
* Proficiency in Cadence development tools and interpretation of verification tools
* Clear understanding of layout considerations, layout parasitics and their impact
* Excellent communication skills and ability to interact effectively with cross-functional teams such as Design, R&D, PDK and Modelling
DESIRABLE
* Solid understanding of a programming language like SKILL, Tcl etc would be beneficial
Candidates who do not meet every requirement but feel their skills are a good fit for the role are encouraged to apply.
Pragmatic is committed to equity, equality, diversity, and inclusion; we strive to welcome everyone and create inclusive teams. We celebrate difference and encourage everyone to be themselves at work. Please let us know if you would like any adjustments to our application and interview process.
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