DFT Design Engineer - Memory Team, Market Drayton
Client: SAMSUNG
Location: Market Drayton, United Kingdom
Job Category: Other
EU work permit required: Yes
Job Reference: cd4974caa4b4
Job Views: 6
Posted: 14.07.2025
Expiry Date: 28.08.2025
Job Description:
Position Summary
Join Samsung's Memory Team as a DFT Design Engineer, working on industry-leading semiconductor solutions including System LSI, Memory, and Foundry technologies. Be part of a global R&D environment focusing on cutting-edge projects such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/6G, Neural processors, and more.
Roles and Responsibilities
* Implement Top/Block, FLAT/Hierarchical DFT insertion flows.
* Execute scan & MBIST insertion, ATPG, and verification at the full chip level.
* Perform timing closure in DFT modes, understanding shift and capture timing constraints, MBIST constraints, and their impacts.
* Generate, review, and validate DFT constraints to ensure timing closure of high-speed designs.
* Experience with RTL analysis, logic synthesis, physical design, and signoff verification (STA, Formality, simulations).
* Exposure to analog and mixed-signal IP tests such as PLLs, MIPI, including pattern generation and verification.
* Support post-silicon bring-up, diagnosis, and debug of logic or memory test failures.
* Understand architecture limitations related to DFT and estimate schedules, tasks, and resources.
* Knowledge of Power Estimation/Management for DFT modes is a plus.
* Mentor junior engineers, support training, collaborate across teams and sites.
* Excellent written and verbal communication skills.
Experience: 5+ Years
Qualifications:
* B.Tech/B.E/M.Tech/M.E
Disclaimer:
Samsung Semiconductor India Research (SSIR) is committed to diversity and equal employment opportunities for all individuals, regardless of background or characteristics protected by law.
Skills and Qualifications:
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