Overview
DDR Subsystem Architecture Engineer is a technical role responsible for ensuring correct implementation of the architecture into cutting edge and complex SoC platforms. This role also involves supporting the architecture to ensure it results in the best performance, lowest power and achieves area efficiency on silicon. The engineer will work with subsystems which use the latest memory technologies that include LPDDR, DDR, HBM and GDDR.
Responsibilities
* Work with DDR subsystem architects to ensure architecture is implemented correctly and efficiently
* Support architectural investigations to help produce best PPA for the subsystem and overall SoC
* Debug performance and functional issues with high-level models, RTL simulation, hard and soft IP
* Work with design, verification, and validation teams to review design specifications & test-plans (pre & post silicon), and support execution teams as required.
You will join a collaborative team working on cutting‑edge DDR, LPDDR, HBM, and GDDR subsystems that power next‑generation SoCs. This role offers the chance to influence architecture and optimisation across the full development lifecycle, from early investigations through post‑silicon debug. You will work closely with architects, designers, and verification teams, with your contributions impacting high‑profile products worldwide. Along the way, you’ll expand your expertise in advanced memory technologies, Arm‑based architectures, and system interconnects while growing your career in a supportive environment.
Arm's approach to hybrid working is designed to create a working environment that supports both high performance and personal well‑being. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team's needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.
Requirements
* Understanding of RTL and familiarity with SystemVerilog or equivalent HDL
* Waveform debug experience on simulation or emulation platforms
* Familiarity with verification processes that include coverage closure, clock domain crossing, lint and more
* Experience with synthesis including understanding timing reports and SDC
* Bachelor's or Master's degrees in Electrical or Computer Engineering and at least 4 years of experience in a senior development position
* Excellent presentation, interpersonal, written, and verbal communication skills
Nice‑to‑haves
* Familiarity with JEDEC specs
* Familiarity with the Arm architecture
* Experience with building DDR subsystems
* Understanding of Arm bus protocols such as CHI, APB, AXI
* Scripting knowledge such as using Python
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