Senior DFT Engineer, Cambridge
We are working with a global semiconductor business, who are developing advanced technologies for connected and intelligent devices; In the heart of Cambridge. The company works across embedded compute, wireless connectivity, sensing, and human interface technologies, supporting the next generation of products used across consumer and commercial markets.
We are seeking a Senior Staff Design for Test (DFT) Engineer to join their growing ASIC team. This role will focus on DFT architecture and the implementation of MBIST, SCAN, and BSCAN for complex SoC's used in Voice Assistant and Multimedia applications.
Key responsabilities:
* Lead DFT architecture and implementation for complex SoCs, with a focus on MBIST, SCAN, and BSCAN.
* Help improve DFT methods and flows to make the team more efficient.
* Support pre-silicon validation of DFT logic at block and full-chip level.
* Optimise DFT logic for power, performance, and area.
* Support static timing closure for test logic across block and full-chip level.
* Work closely with Test Engineering to bring up and validate test patterns on ATE.
What we are looking for:
* Strong understanding of DFT architecture and digital design methods.
* Good communication and problem-solving skills.
* Able to work well with cross-functional and international teams.
* Self-motivated and comfortable working independently.
* Well organised, accurate, and detail-focused.
* Positive and adaptable approach to solving technical problems.
Requirements:
* 7+ years of relevant industry experience.
* Strong hands-on experience with DFT architecture for complex SoCs.
* Experience with Scan/EDT, MBIST, and Boundary Scan.
* Experience creating iJTAG structures in Verilog.
* Strong debug skills using waveforms.
* Experience with Perl scripting for EDA flows.
Interested in hearing more? Please apply!