The Opportunity
We are seeking a Digital Verification Engineer to join our Design Centre in Edinburgh, Scotland or Milan, Italy. The role is critical to Allegro's new product development plans, designing advanced power control ICs for a broad range of product applications. You will be part of a new verification team collaborating on verification of gate‑driver ICs and embedded SoCs based on innovative core architectures.
What You’ll Do
* Develop comprehensive verification plans based on detailed microarchitecture specifications.
* Create and maintain SystemVerilog/UVM‑based verification environments to achieve required coverage metrics.
* Define and create UVM‑SV test environments, test plans, tests, and functional coverage.
* Analyze test results, enhance test coverage, and debug unexpected design behavior.
* Run and maintain regression test suites.
* Prepare and/or lead verification reviews.
* Collaborate with the System Engineering team on JAMA requirements.
* Identify functional coverage conditions derived from microarchitecture specifications.
* Build mixed‑signal testbenches, checkers, and tests.
* Implement constrained random verification methodologies.
* Develop bus‑functional models for verifying custom or industry‑standard interfaces.
* Define project deliverables and tasks, and track their on‑time execution with a strong focus on quality.
Who You Are
* Possess at least a bachelor’s degree in Electrical and/or Electronic Engineering or an equivalent field.
* Proficient in SystemVerilog, Verilog, UVM/OVM, Specman, C/C++, ASM, TCL/TK, and Python.
* Have knowledge of embedded SoC design and verification life‑cycle with emphasis on test plan development, testbench creation, test coverage analysis, and debugging of unexpected design behavior.
* Understand CPU, memory, or I/O subsystem microarchitectures (caches, virtual memory, DMA, memory access optimizations).
* Experience identifying functional coverage conditions based on microarchitecture specifications.
* Experience with SystemVerilog digital using UVM‑SV.
* Expertise in building mixed‑signal testbenches, checkers, and tests.
* Expertise in creating and using real‑numbered analog behavioral models in SystemVerilog/Verilog‑AMS or electrical behavioral models in Verilog‑A.
* Experience in script generation for processing results as well as regression control configuration.
* Experience with constrained random verification.
* Experience with bus‑functional model development for verification of custom or industry‑standard interfaces.
* Experience defining team deliverables and tasks, and tracking on‑time execution with a focus on quality.
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