With mentorship, you will work within the Digital Design Team to refine or create requirements and specifications, collaborate with the analog design and design verification teams, create/update RTL designs, and run simulations to check your design. This could include tasks such as implementing bespoke control of analog circuits, creating state machines to control the system, or working on industry standard interfaces to high performance SoCs. Your designs will need to balance energy efficiency and area constraints with project schedule and maintainability. You may also review synthesis and power reports, root-cause and resolve timing and power issues and ensure maximal QoR throughout your design. Currently pursuing a BS, MS, or PhD in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related field. At the end of the internship, you must return to school to continue your education or the internship must be the last requirement for you to graduate. Coursework focusing on modern, energy-efficient/low-power logic design techniques Strong familiarity with RTL design and understanding of the logic structures being inferred Excellent interpersonal skills and well-organised working style Ability to work well in a team and be productive under tight schedules Strong analytical/problem solving skills An understanding of finite state machines System Verilog language constructs used for RTL design An understanding of CPU bus architectures, and mixed signal design TCL/Perl/Python scripting experience FPGA development experience