Job Responsibilities:
Responsible for layout design and management of analog/mixed signal IP consisting of:
* High-speed and high accuracy Analog Front Ends comprising ADC, DAC and PLL
* Candidate is required to lead and manage delivery of complex analog IP with tasks including floorplan, bump map, IO planning, lef, LVS, ERC, DRC, antenna checks.
* Need to manage schedule and track project plan
Minimum Qualifications
* Bachelor’s degree or equivalent in EE or training in layout design.
* Industry experience of 10 years or more in layout design of analog/mixed signal circuitry.
* Must have direct layout experience in at least two of the following areas: High Speed ADC, DAC, high performance Phase locked loops (LC tank-based designs preferred).
* Experience in 16nm or below technology is must
* Past experience of active participation in at least 2 successful complex analog silicon involving one or more of the above areas.
Preferred Qualifications:
* Deep understanding of floor planning, matching, noise isolation, power supply and signal integrity.
* Project leadership experience on successful complex analog chips.
* Excellent communication skills and ability to work with remote design teams
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