About Us Axelera AI is not your regular deep-tech startup. We are creating the next-generation AI platform to support anyone who wants to help advancing humanity and improve the world around us. In just four years, we have raised a total of $370 million and have built a world-class team of 220 employees (including 49 PhDs with more than 40,000 citations), both remotely from 18 different countries and with offices in Belgium, France, Switzerland, Italy, the UK, headquartered at the High Tech Campus in Eindhoven, Netherlands. We have also launched our Metis™ AI Platform, which achieves a 3-5x increase in efficiency and performance, and have visibility into a strong business pipeline exceeding $100 million. Our unwavering commitment to innovation has firmly established us as a global industry pioneer. Are you up for the challenge? Position Overview We are looking for a Senior/Staff ATE Test Engineer to join our AI accelerator chip team at Axelera AI. You will own the development, optimisation, and deployment of production test programs for our cutting-edge AI accelerator SoCs — from early silicon characterisation through high-volume manufacturing. Working hands-on with external test houses and OSAT partners, you will be the go-to ATE expert within the organisation, directly shaping our ability to deliver quality products at scale. This is your chance to build production test infrastructure from the ground up at a fast-moving AI hardware startup. Why This Role Matters At Axelera AI, production test is the final quality gate before chips reach customers. Every device ships with your work embedded in it. You will have the resources, mandate, and cross-functional access to implement sophisticated test strategies — and the proximity to design and product teams to see your feedback shape future silicon generations. If you want to be the ATE expert at a company building the next wave of AI hardware, this is that role. Key responsibilities: Develop and optimise production test programs covering structural (scan, MBIST, IDDQ), functional, and parametric content for AI accelerator devices. Lead silicon bring-up test activities, characterising device behaviour across voltage and temperature corners to establish robust production test limits and guardbands. Implement scan test insertion, MBIST configuration, and JTAG-based test access, collaborating with design teams to ensure adequate DFT architecture and coverage. Translate functional verification coverage into practical ATE tests for inference engines, memory interfaces, IO, and control logic. Drive test time optimisation through parallelisation, measurement overhead reduction, and elimination of redundant coverage — maximising cost efficiency at volume. Analyse production yield data to identify failure modes, correlate parametric measurements, and close gaps in test coverage or design robustness. Manage technical relationships with test houses and OSAT partners, including program transfer, bring-up support, correlation review, and ongoing production monitoring. Build test automation tooling in Python for data processing, limit tracking, report generation, and workflow automation. Create and maintain comprehensive documentation covering test strategy, coverage rationale, limit derivation, and program architecture. Mentor validation and product engineers in ATE fundamentals, and contribute to methodology improvements across the team. Qualifications: Experience: 7–15 years of hands-on production ATE test engineering, ideally spanning multiple product cycles from first silicon to high-volume manufacturing. ATE Platforms: Deep expertise with at least one major production tester — Advantest 93K/V93K, Teradyne J750/UltraFLEX, or equivalent. Platform-level understanding of instrument allocation, timing constraints, and execution optimisation is essential. Programming: Fluency in ATE-specific environments (IG-XL, SmartTest, C++, or similar) with strong ability to write, debug, and optimise test code for robust production execution. Test Techniques: Solid understanding of digital, analog, and mixed-signal test methodologies for complex SoCs, including high-speed digital interfaces, memory testing, and power management. DFT Knowledge: Practical experience with scan, BIST, and JTAG/IJTAG, with the ability to provide constructive design-for-test feedback during design reviews. Scripting & Analysis: Python (or equivalent) for test automation and data analysis; statistical skills for guardband derivation, yield trend analysis, and outlier detection. Familiarity with JMP, Minitab, or Python statistical libraries is a plus. Device Physics: Working knowledge of CMOS defect mechanisms and parametric variation, informing test strategy beyond simple specification compliance. Bonus: Experience with IEEE 1149.x / 1500 / 1687 standards, OSAT manufacturing integration, or multi-site test execution. Strong ownership mindset, attention to detail, and the ability to collaborate across design, validation, product, and manufacturing teams. Location This position is based in Bristol on an on-site/hybrid basis, What we offer This is your chance to shape and be part of a dynamic, fast-growing, international organization. We offer an attractive compensation package, including a pension plan, extensive employee insurances and the option to get company shares. An open culture that supports creativity and continual innovation is awaiting you. Collaborative ownership and freedom with responsibility is characteristic for the way we act and work as a team. At Axelera AI, we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. Our steadfast commitment is to cultivate a warm and inclusive environment that empowers and celebrates every member of our team. We welcome applicants from all backgrounds to join us in shaping the future of AI.