Key Responsibilities:
Research and develop next-generation data prefetching techniques including ML-based predictors and irregular access pattern prediction.
Design advanced speculative execution mechanisms and thread-level speculation (TLS).
Research branch prediction innovations including neural branch predictors, path-based prediction, slice-based prediction, and conditional control flow slice techniques.
Design ISA extensions and microarchitectural support for compiler-directed optimizations including software pipelining and instruction scheduling hints.
Propose microarchitectural support for JIT compilation, dynamic optimization, and adaptive execution.
Design simulation and prototyping frameworks integrating compiler toolchains with architectural models for microarchitectural evaluation.
Participate in joint research projects with top tier UK universities, compiler teams, and OS kernel developers on future processor architectures.
Requirements:
Master/PhD degree in Computer Science/Engineering/Physics etc.
Strong knowledge of advanced computer architectures, superscalar processor design, and compiler design principles.
Deep understanding of speculative execution, branch prediction, and out-of-order execution.
Strong programming skills in C, C++, Python, assembly languages (Arm64 assembly or RISC-V assembly), and scripti...