Overview
A market-leading EDA company is looking for an experienced Engineer to come and join their Application Engineering team in Cambridge. This is a fantastic opportunity for a Formal Verification Engineer to progress into a more customer-facing role, as you will interact closely with the R&D team and the customer.
In this role, you will have a fantastic opportunity to expand your Formal Verification skills and work closely with a leading-edge customer!
Responsibilities
* Interact closely with the R&D team and the customer to support formal verification efforts.
* Expand your Formal Verification skills while working with a leading-edge customer.
Qualifications
* Bachelor or Masters in Electronic Engineering or a related field
* Proven technical experience in Jasper Gold, OneSpin, or VC Formal is essential
* Knowledge of Verilog, System Verilog or VHDL
* Involved in several tapeouts at multiple technology nodes
Details
* Location: Cambridge, England, United Kingdom
* Seniority level: Mid-Senior level
* Employment type: Full-time
* Job function: Staffing and Recruiting
Contact
* Tel - 01189073075
* LinkedIn - https://www.linkedin.com/in/jordan-browne-b4a08b20b/
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