Your tasks will include: - Develop your expertise in ASIC verification by working with a best-in-class Design Verification team to create verification plans, develop stimulus, define verification strategy and completeness metrics - Implement various components of the verification environment and participate in debugging test-bench code as well as deep design debug - Where applicable, run simulations with synthesized netlist and analyse/debug any issues encountered - Collaborate with the architecture and design teams to ensure any potential issues/critical cases are considered and dealt with as early as possible in the design cycle Currently pursuing a BS, MS, or PhD in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related field. At the end of the internship, you must return to school to continue your education or the internship must be the last requirement for you to graduate. Strong familiarity with understanding RTL design in Verilog/VHDL and logic structures being inferred Very good understanding of OOP basics and experience/exposure of using HDLs/HVLs such as SystemVerilog and/or UVM Excellent interpersonal skills and well-organised working style Strong analytical/problem solving skills Ability to work well in a team and be productive under tight schedules Knowledge of finite state machine, CPU bus architectures and mixed signal design/verification is desirable TCL/Perl/Python scripting experience/exposure