Job Description:
Role: Senior IP Design Engineer Type: Contract Location: Belfast, UK Hybrid
Job details: Design high-performance IP targeting FPGA/Adaptive SoC technology using SystemVerilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements.
Key Skills: SystemVerilog RTL design 100Gb Ethernet, PCIe Gen5, AMBA/AXI Deep understanding of FPGA/Adaptive SoC design flow including click apply for full job details