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ARM’s hardware is at the heart of the computing and connectivity revolution that continues to transform the way people live and businesses operate.
This position offers an excellent opportunity for an experienced and highly motivated design engineer to join the hardworking System IP team!
This is a fast-paced technical role employing the latest hardware design methodologies to develop complex and highly configurable hardware IP that sit at the heart of Arm-based Systems!
The Interconnect team develops the Arm Corelink Interconnect IP family. Our Interconnects and NoCs are designed for intelligent connected systems across various applications including mobile, IoT, networking infrastructure, automotive, etc. The highly scalable IP is optimized for AMBA-compliant SoC connectivity and can be customized for multiple performance points.
Responsibilities:
* Analyze proposed specifications to understand implementation challenges and opportunities, working with architects to improve and refine ideas.
* Plan, track, and coordinate tasks for yourself and your team.
* Collaborate with modelling, verification, performance analysis, and back-end implementation colleagues to ensure your design meets all functional and performance requirements.
* Improve design methodology to meet evolving needs.
You will be responsible for developing one or more functional blocks of the IP, requiring an in-depth understanding of all aspects of successful product delivery, including low-power design techniques, system performance impact, area-efficient designs, and verification techniques to ensure high-quality, innovative outputs.
Required Skills and Experience:
* Proven track record of delivering high-quality, low-power, high-performance micro-architecture and RTL design using System Verilog, Verilog, or VHDL within reasonable timescales.
* Ability to make high-level design trade-offs and articulate the rationale behind decisions.
* Knowledge of ASIC (or FPGA) design methodology, IP signoff processes, and understanding of timing, area, and complexity trade-offs for complex data path designs.
'Nice To Have' Skills and Experience:
* Team leadership and mentoring experience.
* Knowledge of memory system interconnect protocols (AMBA ACE-Lite or AXI).
* Solid understanding of SystemVerilog Assertions (SVA) and formal verification.
* Experience with scripting languages such as Perl, Tcl, or Python.
* Experience working on Functional Safety product development for the Automotive market, applying standards such as ISO 26262 and IEC 61508.
In return -
You will utilize your engineering skills to build support for technologies that influence millions of devices for years to come!
Accommodations at Arm
At Arm, we support our people to Do Great Things. If you need support or accommodations during the recruitment process, please email us. By providing your information, you consent to its use for arranging accommodations. All requests are confidential and only disclosed as necessary. Examples include interview breaks, document reading, or office accessibility. Please contact us for more details.
Hybrid Working at Arm
Our hybrid approach offers flexibility, balancing office and remote work. Specific arrangements depend on the role and team needs, and details will be shared upon application. We aim to accommodate local legal, regulatory, or logistical considerations to find the best solution for each candidate. Please reach out to learn more.
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