A fast-growing deep-tech company working at the intersection of advanced hardware, software, and cutting-edge research is hiring a Senior/Staff Digital Design Engineer. Backed by significant funding and working closely with leading industry and research partners worldwide, the company is building highly innovative systems. The team is growing rapidly and offers a rare opportunity to work on genuinely frontier technology. I am seeking an experienced Digital Design Engineer to join a growing hardware team developing a highly complex, low-latency, high-throughput compute platform. They are building the world’s first quantum error correction (QEC) stack. While prior experience in this specific application domain is not required, strong classical digital design skills are essential, and you will gain exposure to new technologies as part of the role. At senior level, you will play a key role in designing and optimising a multi-FPGA system required to perform complex operations deterministically and at very high performance. You will contribute to architecture decisions, support and mentor junior engineers, collaborate closely with software teams, and help identify innovative solutions to challenging technical problems. The environment is fast-paced and collaborative and they are moving fast in a brand new market, where requirements can change quickly as the technology evolves, so the ability to adapt is critical. As a Senior/Staff Digital Design Engineer you will work on: Performance and area optimisation of complex RTL designs Design of deeply pipelined modules capable of operating at very high clock frequencies Review of specifications and RTL developed by junior engineers Contribution to system-level architecture and design decisions Required experience Proven professional experience in one or more of the following areas: Implementation of modern decoding or signal-processing algorithms on FPGA or ASIC SoC architecture involving CPUs and custom hardware accelerators Large-scale, complex FPGA or ASIC-based systems Experience with modern FPGA platforms Strong capability in testing, debugging, and improving complex digital systems Ability to translate high-level product requirements into clear technical specifications Experience working in ASIC design environments (sub-48nm process nodes) On offer is a comprehensive benefits package which includes equity, base and bonus as well as private medical and various insurances. Visa sponsorship can be given if required, but you must be willing to be onsite in the office in Cambridge 3 days per week. For more information, contact Rachel Mason at IC Resources.