In this role you will develop verification plans in coordination with design leads and architects. You’ll be responsible for building and maintaining verification test bench components and environments. Generate directed and constrained random tests. Run simulations and debug design and environment issues. Build functional coverage points, analyze coverage, and improve test environment to target coverage holes. Craft automated verification flows for block and chip level verification. Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM/OVM/VVM), and logic simulators to verify complex designs. Work with other block and core level engineers to ensure a flawless verification flow. Strong knowledge of SystemVerilog and UVM Experience developing scalable and portable test-benches Experience with constrained random verification environments MS/BS in Computer Science or Electrical Engineering or equivalent Fluency in English language is required Experience defining coverage space, writing coverage model, analyzing results Experience with Assertion Based Verification Knowledge of Object Oriented Programming Experience in Formal Verification (Formal Linting, Formal connectivity, user property verification) Experience with Python, Perl or TCL Excellent communication and interpersonal skills combined with the ability to collaborate Basic knowledge of mixed signal verification Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants