Our Edinburgh based client is dedicated to providing cutting-edge network monitoring solutions.
About the Role
Reporting to the R&D Project Manager, candidates will be responsible for the architecture, design and verification of FPGA sub-systems within our client's flagship network monitoring products. The role is multi-disciplinary and includes development of FPGA IP Cores, full FPGA System-on-Chip RTL designs and verification testbenches.
Responsibilities
* Architecture, design and verification of FPGA sub-systems.
* Development of FPGA IP Cores.
* Full FPGA System-on-Chip RTL designs.
* Verification testbenches.
* Mentoring of less experienced colleagues (for senior roles).
Beneficial Skills to have
* Experience of designing FPGA IP cores or sub-systems.
* Designing FPGA architectures from a technical specification.
* Design with AMD/Intel FPGA and CPLD devices.
* Using VHDL/Verilog HDL languages for FPGA design.
* Implementing high speed, multi-frequency clocking architectures.
* Designing (code entry to timing analysis) using Intel and/or Xilinx FPGA tool sets.
* Designing for high-speed optical interfaces.
* Designing for high-speed SERDES interfaces (up to 28G/56G).