Job Description
We are looking for an experienced packaging designer to develop creative and cost‑effective packaging designs.
Responsibilities
* Netlist creation, BGA creation as per the inputs
* Conduct feasibility studies to advise optimum pad layout, interconnect types and substrate parameters for a specific IC device or application.
* Define substrate stack‑ups, routing strategies and via structures.
* Substrate design experience for RF, digital, high‑speed and mixed signal die.
* Excellent understanding of SI/PI requirement for routing HSIO (DDR, SERDES, etc.).
* Good experience in UCIE-Advanced and Standard technology, HBM technology.
* Experience in setting design rule checks (DRC) to ensure layouts meet specific manufacturing, Assembly and design guidelines.
* Experience of optimising the die breakout for signals and create patterns for high power.
* Strong understanding of HDI substrate technologies, layout design rules, and materials for optimal performance. Verify designs against electrical, thermal, mechanical, and manufacturability requirements.
* Hands‑on experience with Wire bond, Flip chip & advanced packaging technologies (2.5D, 3D, RDL, embedded passives, etc.)
* Strong experience with CoWoS (Chip‑on‑Wafer‑on‑Substrate) interposer design and the impact of the substrate design to support CoWoS.
* Knowledge of different OSAT design rules.
Qualifications
* Bachelor’s degree in Electronics / Electrical Engineering.
* 5+ years in IC package design and development.
* Proficiency with Cadence Allegro Package Designer.
Seniority level
* Mid‑Senior level
Employment type
* Contract
Location
* Cambridge, England, United Kingdom
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