Job Description:Role: Senior IP Design EngineerType: ContractLocation: Belfast, UK HybridJob details:Design high-performance IP targeting FPGA/Adaptive SoC technology using SystemVerilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements.Key Skills:SystemVerilog RTL design100Gb Ethernet, PCIe Gen5, AMBA/AXIDeep understanding xxuwjjq of FPGA/Adaptive SoC design flow including
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