Axelera AI is a deep‑tech startup building a next‑generation AI platform that supports anyone looking to advance humanity and improve the world. In just four years we raised $120 million, built a team of 220+ employees (including 49+ PhDs), and launched the Metis™ AI Platform, which delivers a 3‑5× increase in efficiency and performance.
Position Overview: We’re seeking an experienced R&D engineer specialized in CPU architecture. The ideal candidate has deep expertise in CPU design, analysis and modeling, with a keen understanding of performance‑power‑area trade‑offs. Experience integrating architectural features into major ISAs (RISC‑V, ARM, x86) is highly advantageous.
You will independently evaluate architectural proposals, develop innovative improvements or implementations, and ensure they meet evolving AI training and high‑performance computing needs.
Key responsibilities:
* Design & analysis of CPU microarchitectural components (pipelines, fetch/decode, branch prediction, caches, memory hierarchy, OoO/rename/issue, interconnects, SIMD/vector/matrix units) and optimization of PPA trade‑offs for AI, HPC, and cloud workloads.
* Modeling & simulation: Build and validate performance/functional models, run simulations, and correlate results to RTL to guide architectural decisions.
* ISA implementation: Develop and evaluate architectural extensions within RISC‑V; assess performance, programmability, and toolchain compatibility.
* Innovation & prototyping: Propose, model, and prototype new mechanisms to improve efficiency, scalability, and performance.
* Collaboration & research: Work closely with hardware, compiler, and system teams to align roadmaps and enable new capabilities. Stay ahead of trends in CPU, memory, interconnect, and AI‑adjacent architectures.
Qualifications:
* MS/PhD in CE/EE/CS (or related field) with a focus on CPU architecture or microarchitecture.
* Deep expertise in CPU design, PPA optimisation, and ISA extensions (RISC‑V, ARM, x86).
* Skilled in performance modeling and simulation (e.g., gem5, ChampSim, Sniper, QEMU), cycle‑accurate and trace‑driven analysis, and correlation to RTL.
* Experienced in benchmarking and workload characterization (SPEC, MLPerf, or internal suites).
* Proficient in RTL design and validation (Verilog/SystemVerilog/Chisel), including simulation, synthesis, and FPGA/emulation bring‑up.
* Knowledge of compiler/toolchain integration, low‑level software (C/C++/assembly), Linux kernel/driver development, and performance tuning for ISA features.
* Strong analytical, collaborative, and communication skills with proven ability to drive architectural proposals from concept to validation.
* Fluent in English.
* Able to work from one of our European offices or remotely, preferably based in Bavaria (Munich), Belgium, or Italy.
Location:
* Work from one of our European offices (Leuven in Belgium, Amsterdam and Eindhoven in the Netherlands, Zurich in Switzerland, Florence and Milan in Italy, or Bristol in the United Kingdom) if you’re already based nearby.
* Work fully remotely from any European country (incl. the UK) you’re already in.
* Relocate with us to Italy (Florence or Milan), Belgium (Leuven) or the Netherlands (Amsterdam or Eindhoven).
Priority will be given to candidates based in Bavaria (Munich), Belgium or Italy.
What We Offer:
Compensation package including a pension plan, extensive employee insurances, and the option to receive company shares. An open culture that supports creativity and continual innovation awaits you. Collaborative ownership and freedom with responsibility are characteristic of how we act and work as a team.
At Axelera AI, we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. Our steadfast commitment is to cultivate a warm and inclusive environment that empowers and celebrates every member of our team.
Seniority level: Mid‑Senior level
Employment type: Full‑time
Job function: Design, Art/Creative, and Information Technology
Industries: Semiconductor Manufacturing
#J-18808-Ljbffr