Senior CPU Research Engineer – Contractor at Huawei Technologies Research & Development (UK) Ltd
Overview
Huawei Research & Development UK Limited is a leading R&D organization within Huawei’s global network, operating design centers in Cambridge, London, Edinburgh and Ipswich. The company focuses on advancing digital connectivity, AI, cloud, and next‑generation computing technologies.
Key Responsibilities
* Research and develop next‑generation data prefetching techniques including ML‑based predictors and irregular access pattern prediction.
* Design advanced speculative execution mechanisms and thread‑level speculation (TLS).
* Research branch prediction innovations including neural branch predictors, path‑based prediction, slice‑based prediction, and conditional control flow slice techniques.
* Design ISA extensions and microarchitectural support for compiler‑directed optimizations including software pipelining and instruction scheduling hints.
* Propose microarchitectural support for JIT compilation, dynamic optimization, and adaptive execution.
* Design simulation and prototyping frameworks integrating compiler toolchains with architectural models for microarchitectural evaluation.
* Participate in joint research projects with top‑tier UK universities, compiler teams, and OS kernel developers on future processor architectures.
Required Qualifications
* Master’s/PhD degree in Computer Science, Engineering, Physics or related field.
* Strong knowledge of advanced computer architectures, superscalar processor design, and compiler design principles.
* Deep understanding of speculative execution, branch prediction, and out‑of‑order execution.
* Strong programming skills in C, C++, Python, assembly languages (Arm64 or RISC‑V), and scripting languages.
* Experience with cycle‑accurate microarchitecture simulation and performance modeling.
* Understanding of instruction scheduling, register allocation, and code generation.
* Highly‑motivated and independent individual with a strong desire for knowledge acquisition.
Desired Skills
* Strong knowledge of advanced branch predictors and prefetching mechanisms.
* Experience with gem5, Sniper, ChampSim, or other cycle‑accurate detailed microarchitecture simulators.
* Experience with LLVM backend development or custom ISA extension implementation.
* Strong knowledge of profile‑guided optimization (PGO) and feedback‑directed optimization.
* Experience with compiler development (LLVM, GCC) or compiler optimization techniques.
* Experience with OS kernel development and understanding of scheduler and memory manager internals.
* Knowledge of binary translation, dynamic binary instrumentation, or JIT compilation techniques.
* Understanding of hardware‑enforced security mechanisms (CFI, PAC, BTI, MTE on Arm).
* Experience with co‑simulation frameworks integrating ISA simulators with compiler toolchains.
* Familiarity with emerging technologies: processing‑in‑memory (PIM), near‑data processing, chiplet architectures.
* Familiarity with domain‑specific architectures and accelerator‑compiler co‑design methodologies.
Location
Cambridge, England, United Kingdom
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