Company
Qualcomm Technologies International Ltd
Job Area
Engineering Group, Engineering Group > ASICS Engineering
General Summary
A world leader in smart mobile technologies, Qualcomm offers complete solutions that enable continuous innovation for today's smart connected devices. Our vast expertise in wireless technology, combined with our unique systems approach to developing solutions, puts Qualcomm at the forefront of the rapidly expanding mobile industry.
This role offers a Power Lead position within the Audio Digital Design team, responsible for driving power analysis, and identifying power optimisations for Audio IP. The Power Lead will work closely with Digital Design but also Physical Design, Systems, Firmware, Verification, and Analog teams to ensure power targets are anticipated, measured, and met early and throughout the design cycle.
Based out of Qualcomm’s Cambridge or Bristol UK office, you’ll be joining a collaborative and well‑established engineering organisation with deep expertise in digital design, verification, and systems development, whose deliveries can be found in billions of Voice and Music, IoT and mobile products worldwide.
Key Responsibilities
* Translate customer use‑cases into power targets at IP level, identifying simulation use‑cases needed to drive power analysis tools.
* Maintain and refine the IP level power methodology, including PTPX/PowerArtist tools and analysis.
* Drive IP‑level power analysis and optimizations across audio IP, through all phases of IP and SoC development. Feed actionable recommendations back to design teams.
* Identify power hotspots and prioritise optimisation effort based on impact, usage frequency, and architectural stability.
* Work with IP leads to drive high‑level power analysis during early design phases.
* Support the design team identify RTL power optimisation: clock gating, data path activity reduction, memory and interface optimisation, and low‑power state behaviour.
* Collaborate with Analog, DV and FW teams to ensure end‑to‑end power validation aligns with real product use‑cases.
* Accurately report power status to project leads and cross‑functional discussions.
* Mentoring less experienced engineers.
* Communicate status, risks and trade‑offs clearly to engineering and management stakeholders.
Minimum Qualifications
* Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
* Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
* PhD in Science, Engineering, or related field.
Required Competencies
* Experience in digital power analysis and optimisation for SoCs or complex IP.
* Strong hands‑on experience with PTPX, Power Artist or equivalent RTL/Gate level power tools.
* Experience with multi‑voltage, low‑power design using Cadence CLP or Synopsys VC‑LP tools and creation of UPF/CPF.
* Solid understanding of digital design principles (clocks, resets, CDC, power domains).
* Ability to translate system level use cases into meaningful test scenarios for power analysis.
* Ability to analyse data and present clear conclusions to influence design decisions.
* Excellent communication skills with the ability to explain complex power behaviour clearly.
* Ability to work autonomously while coordinating across multiple teams and programs.
* Proactive and creative, with a strong desire to continuously improve designs, processes, overall team effectiveness and delivery execution.
Education Requirements
* Bachelor’s degree in Electrical/Electronic Engineering or equivalent degree.
* References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.
Qualcomm is an equal opportunity employer.
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