We tackle the most complex problems in quantitative finance, by bringing scientific clarity to financial complexity. From our London HQ, we unite world-class researchers and engineers in an environment that values deep exploration and methodical execution - because the best ideas take time to evolve. Together we’re building a world-class platform to amplify our teams’ most powerful ideas. As part of our engineering team, you’ll shape the platforms and tools that drive high-impact research - designing systems that scale, accelerate discovery and support innovation across the firm. Take the next step in your career. The role G-Research is seeking a Design Verification Engineer to join our world-class Software Engineering function. As a Design Verification Engineer, you will provide technical expertise, support and guidance around formal verification tools. Working within our client’s methodology and flows, you will oversee the effective application of formal verification. You will have excellent knowledge of industry standard interfaces and build tools, and be comfortable writing test plans, creating test benches and analysing code coverage. Key responsibilities of the role include: Developing System Verilog based VMM/UVM test bench environments Developing assertion based formal verification Developing co-simulation environments to verify between C/C++ models and RTL modules Writing test plans, creating test bench specifications and analysing code coverage plans Implementing constrained-random sequences, agents and environments using the UVM methodology Developing and maintaining complex verification environments using different methodologies, such as UVM and SV Who are we looking for? We are looking for an engineer with extensive experience of large FPGA and ASIC design to join our Software Engineering function. The ideal candidate will have the following skills and experience: Knowledge of industry-standard interfaces, such as Avalon and AXI Experience with industry-standard build tools, including version control Knowledge of QuestaSim environment Must have extensive experience with large FPGA/ASIC designs A background in fintech would also be beneficial Why should you apply? Highly competitive compensation plus annual discretionary bonus Lunch provided (via Just Eat for Business) and dedicated barista bar 35 days’ annual leave 9% company pension contributions Informal dress code and excellent work/life balance Comprehensive healthcare and life assurance Cycle-to-work scheme Monthly company events