We are seeking an experienced Hardware Emulation Engineer to lead the deployment, optimization, and debug of large‑scale SoC designs on hardware emulation platforms such as Cadence Palladium, Synopsys ZeBu, or Siemens Veloce. You will collaborate closely with design, verification, software, and validation teams to accelerate pre‑silicon bring‑up, software development, and system‑level performance analysis. As a senior contributor, you will also mentor junior engineers, drive emulation best practices, and help define flows that improve debug efficiency and turnaround time.
Responsibilities
* Lead emulation compilation, partitioning, mapping, and bring‑up of complex SoC and subsystem RTL designs.
* Develop and maintain emulation flows and scripts (TCL, Python, Makefiles) to automate compile, load, and regression runs.
* Interface with RTL, verification, and firmware teams to integrate new IP blocks, clocking structures, and memory models into emulation.
* Configure and manage emulation platforms (Cadence Palladium Z3, Synopsys ZeBu EP, etc.).
* Implement transactors, virtual bridges, and hybrid co‑simulation with host environments for software execution.
* Debug issues at RTL, waveform, and system levels, including reset sequencing, boot flows, and I/O interfaces.
* Support pre‑silicon software bring‑up (bootloaders, drivers, OS) and ensure timely availability of emulation models to software teams.
* Collaborate with verification engineers to map verification testbenches to emulation platforms or acceleration environments.
* Work with EDA vendors to evaluate and deploy new emulator features and performance optimizations.
* Mentor junior engineers and provide technical guidance on emulation methodologies.
Hybrid Working
Arm's approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team's needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.
Qualifications
* B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
* 8+ years of experience in ASIC/SoC verification or emulation.
* Hands‑on expertise with at least one major emulation platform: Cadence Palladium (Z2/Z3), Synopsys ZeBu, or Siemens Veloce.
* Strong RTL knowledge (SystemVerilog / Verilog / VHDL) and familiarity with synthesis and timing concepts.
* Proficient in debug tools and waveform analysis (SimVision, Verdi, or DVE).
* Working knowledge of transactors and interfaces (AXI, AHB, APB, PCIe, DDR, USB, Ethernet, etc.).
* Skilled in C/C++, scripting and automation (Python, Perl, or TCL).
* Solid understanding SystemVerilog testbenches and acceleration integration.
* Experience with SoC boot flows, firmware loading, and hybrid co‑simulation.
* Excellent problem‑solving and cross‑team collaboration skills.
* Experience with hybrid emulation (Palladium/Protium) or FPGA prototyping flows.
* Knowledge of performance and power validation in emulation environments.
* Experience with multi‑clock domain designs and CDC debug.
* Exposure to post‑silicon bring‑up and correlation with emulation results.
* Familiarity with CI/CD automation (Jenkins, GitLab CI) for emulation regression management.
* Leadership experience mentoring junior engineers or managing small teams.
Key Success Attributes
* Strong ownership and ability to deliver under tight schedules.
* Ability to drive complex SoC debug through detailed analysis and cross‑team coordination.
* Continuous improvement mindset for emulation performance, stability, and usability.
* Excellent communication and documentation skills.
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