A leading semiconductor solutions provider in Edinburgh seeks a Staff Design Verification Engineer to ensure the functional correctness of complex digital and mixed-signal ASIC designs. You will develop verification plans, create testbenches using SystemVerilog/UVM, and mentor junior engineers in a collaborative environment. Candidates should have over 10 years of experience in verification, strong proficiency in SystemVerilog and UVM, along with a relevant degree. A hybrid work model is offered, emphasizing innovation and teamwork.
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