FPGA Developer : Data Acquisition System for High:Energy X:ray Imaging
Location: Remote or Hybrid (On:site optional)
Start Date: ASAP
Duration: 8:12 weeks (per engineer)
Contract Type: Freelance / Contractor
Rate: Competitive (based on experience)
Primary Tools: Verilog, Altera MAX 10, Quartus Prime
Team Size: 2 FPGA Engineers (working closely with project lead)
Project Overview:
We are seeking two experienced FPGA Engineers to support the development of a high:speed data acquisition system for next:generation high:energy X:ray imaging solutions. The system will be deployed in AI:driven railway inspection applications where large:format sensor arrays scan moving trains for security and safety analysis.
The project requires two concurrent FPGA designs targeting Intel (Altera) MAX 10 FPGAs : one for a Sensor Card and one for a Readout Card : operating together in a distributed acquisition architecture.
Key Responsibilities:
Each engineer will be responsible for the design, implementation, and integration of Verilog:based RTL targeting the Altera MAX 10 platform. The two engineers must collaborate closely, sharing common IP and adhering to a coordinated development and test plan managed via Quartus Prime.
System Architecture Summary:
:Sensor Array: Typically up to 85 sensor cards in a daisy:chained string
:Data Rate: 400 projections per second
:Interface: 50MHz DDR LVDS between cards
:Data Output: UDP Jumbo Packets via 1000Base:T EthernetSensor Card FPGA : Key Functional Blocks:
:Interface to ADC and analog front:end (serial data 20 MHz) with SPI configuration
:Dual:port memory for reordering non:sequential to sequential data
:A/B memory buffering for acquisition and readout interleaving
:LVDS DDR I/O (50 MHz) to/from neighbouring cards
:Half:duplex UART communication up/down the sensor chain
:Composite SYNC pulse decoder (extracts projection number, gain settings, etc.)
:Timing and Control logic
:In:system reprogramming capabilityReadout Card FPGA : Key Functional Blocks:
:LVDS DDR interface to the final sensor card (50 MHz)
:Gigabit Ethernet (1000Base:T) interface to host PC
:Half:duplex UART interface to final sensor card
:SYNC pulse generator with encoded metadata
:Receive buffer for incoming Ethernet command messages
:Transmit buffer for outgoing data and responses via Ethernet Jumbo packets
:In:system reprogramming capabilityRequirements:
Essential:
:Exper