FPGA Firmware Engineer – Ulverston Hybrid or Remote (3 days on site per month, Tuesday to Thursday). Travel and accommodation fully expensed.
Responsibilities
* FPGA Architecture & Real‑Time Signal Processing:
o Develop FPGA designs for multi‑channel acoustic data acquisition, digital down conversion, filtering (FIR/IIR), FFT processing, beamforming algorithms, pulse compression and matched filtering.
o Implement high‑speed streaming data pipelines.
o Optimize fixed‑point arithmetic for deterministic real‑time performance.
o Design low‑latency architectures for active sonar systems.
* High‑Speed Interface Development:
o Implement and validate interfaces: high‑speed ADC/DAC, JESD204, LVDS, SERDES.
o Develop memory interfaces (DDR3/DDR4) for buffering high‑bandwidth acoustic data.
o Ensure deterministic timing and synchronization (e.g., PTP, trigger alignment).
* Hardware Integration & Subsea Considerations:
o Collaborate with analogue and hardware engineers on front‑end acoustic transducer electronics, low‑noise acquisition chains, clocking strategies, and jitter management.
o Consider power efficiency and thermal constraints in sealed subsea systems.
o Contribute to design for reliability in harsh marine environments.
* Verification, Testing & Validation:
o Develop simulation testbenches for signal processing chains.
o Perform bit‑accurate modelling (MATLAB/Python to RTL correlation).
o Conduct hardware bring‑up and debug using integrated logic analyzers, oscilloscopes, spectrum analyzers.
o Support acoustic tank testing and sea trials where required.
* Performance Optimisation:
o Achieve timing closure for high‑speed DSP architectures.
o Optimize FPGA resource usage (DSP slices, BRAM, LUTs). Minimise latency in signal paths.
o Improve power efficiency for long‑duration subsea deployments.
* Documentation & Compliance:
o Produce design documentation and verification reports.
o Support compliance with relevant standards (EMC, CE, marine, defense).
o Participate in design reviews and risk assessments (FMEA).
Requirements
* Strong proficiency in VHDL and/or Verilog.
* Experience with Xilinx (AMD) or Intel FPGAs.
* Strong understanding of digital signal processing, fixed‑point arithmetic, FFT and filtering implementations, multi‑rate signal processing.
* Experience with high‑speed ADC/DAC interfacing.
* Knowledge of clock domain crossing and timing constraints.
* Familiarity with MATLAB or Python for DSP modelling.
* Degree in Electronic Engineering or related discipline.
* Postgraduate study in DSP, acoustics, or embedded systems (advantageous).
Key Performance Indicators
* Successful real‑time processing at required bandwidth.
* Timing closure at target clock frequencies.
* Low defect rate in sea trials.
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