Our ideal candidate will be responsible for developing high-speed network interface cards as an FPGA Design Engineer. Key responsibilities include microarchitecture definition, RTL implementation, synthesis and timing closure, verification and testing using SystemVerilog, and delivering and validating FPGA-based lab setups for trials.
The successful candidate will have a strong understanding of clock domain crossing techniques and experience with FPGA tool flows (synthesis, partitioning, place and route, timing analysis). They will also possess excellent skills in SystemVerilog/Verilog/VHDL, scripting in Python/Tcl, and driver expertise.
The role offers the opportunity to work on exciting technologies and be part of a great team working environment in new offices. A good relevant degree is required, along with extensive hands-on industry experience of FPGA design for network applications at 100Gbps and above.
In this position, you will have the chance to utilise your knowledge of PCIe, CXL, RDMA, DDR4, bare metal use of high-speed transceivers, Ethernet, IP, and other related technologies to drive innovation in the field of data centre technologies.