Design for Test (DFT) Engineer - Be at the Forefront of AI and Semiconductor Innovation
Location: Remote within Europe or on-site in the Netherlands
The Role: Are you ready to push the boundaries of AI and semiconductor technology? Join a high-calibre team of engineers in a pioneering AI start-up that’s transforming the industry with cutting-edge, high-performance solutions. As a Design for Test (DFT) Engineer, you will play a pivotal role in architecting and implementing testability infrastructure for our multicore in-memory-compute System on Chip (SoC) – technology that is redefining performance and efficiency in AI.
Your Responsibilities as a Design for Test (DFT) Engineer:
* Develop and execute advanced DFT strategies for multicore in-memory-compute SoCs.
* Collaborate closely with cross-functional teams to deliver seamless and innovative test solutions.
* Lead advancements in testability methodologies, continuously optimising for efficiency and performance.
What We’re Looking For in a Design for Test (DFT) Engineer:
* Proven Expertise in DFT engineering, with a strong record of technical innovation.
* Technical Proficiency : Skilled in SystemVerilog RTL, TCL, Python, and Unix/Linux environments.
* Core DFT Competencies : Experience with hierarchical scan, memory BIST, JTAG/IJTAG, at-speed testing, ATPG, fault simulation, and silicon debug.
* Tools Experience : Familiarity with Siemens, Cadence, and Synopsys DFT tools.
* Problem-Solving Skills : Exceptional troubleshooting and debugging abilities.
* Communication Skills : Fluent in English, with a collaborative approach to complex technical discussions.
Ready to Shape the Future? If you’re an innovative problem-solver who is passionate about pushing technological boundaries, this is your chance to join as a Design for Test (DFT) Engineer. Join a culture that celebrates creativity, collaboration, and excellence in semiconductor technology.
If you are interested in finding out more, or applying for this position, please contact Rachel Mason at IC Resources.