Overview
For this role we are looking for engineers who are capable of owning the verification of a unit within a project through all phases of the design and verification flow. This includes:
Responsibilities
* Working closely with the RTL design team to develop comprehensive verification strategies
* Creating and reviewing design verification documentation
* Designing and implementing SystemVerilog/UVM based verification IP and testbenches
* Improving existing testbenches to increase performance, quality and efficiency
* Testing and debugging Verilog RTL
* Defining and implementing functional coverage as well as enhancing the testbench to ensure coverage closure
* Planning and tracking tasks to meet the targets at the planned time
* Driving the execution to ensure the quality of the design work done, along with on-time delivery
* Coaching and mentoring junior engineers
* Coaching and mentoring juniors in line with Arm's hybrid working approach, which supports both high performance and personal wellbeing. Details of what this means for each role will be shared upon application. In some cases, flexibility may be limited by local legal, regulatory, tax, or other considerations.
* This position provides an outstanding opportunity for a highly motivated and experienced verification engineer to join the System IP team
* Substantial experience in RTL verification of complex ASIC products
* Proficiency in a hardware verification language, preferably SystemVerilog/UVM
* Experience in the development of coverage-driven constrained random test environments
* Experience producing specifications and documentation describing complex designs
* Understanding of the fundamentals of computer architecture
* Strong communication skills and ability to work well as part of a team
Nice to have Skills and Experience
* Scripting languages such as Python or Perl
* Exposure to all stages of the design cycle: initial concept, specification, implementation and testing, documentation and support
* Understanding of object-oriented programming, data structures, and algorithms
* Knowledge of formal verification techniques and tools
* Hardware design language, preferably Verilog
About the Team and Location
The Arm Central Engineering - System IP group in Cambridge is responsible for specifying, developing and validating IP products from the Arm CoreLink and CoreSight IP portfolio, responsible for interrupt control, inter-process communication, trace, and debug solutions. These IPs are a crucial part of systems that scale from real-time embedded to hyperscale cloud. This role will be based at Arm's corporate headquarters in Cambridge, UK, a city known for global innovation and home to a world-renowned university. As Arm's largest engineering centre, the Cambridge site works on development across Arm's product portfolio. If you are excited by cutting-edge technology and meet the requirements of the job description, we look forward to receiving your application.
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