Junior Development Verification Engineer (Training and Progression)
Find out exactly what skills, experience, and qualifications you will need to succeed in this role before applying below.
£30,000 - £35,000 + Training + Progression + 10% Bonus
Bristol - Hybrid
Are you an aspiring Verification Engineer looking to grow your expertise in SystemVerilog and UVM within a world-leading semiconductor company offering industry-leading training, structured progression, and the opportunity to increase your earnings through a 10% company bonus?
This leading semiconductor and microcontroller provider supplies innovative solutions into the automotive and industrial sectors worldwide. With a turnover in the billions and a strong global presence, they support clients in driving efficiency, safety, and sustainability across critical industries.
In this role, you'll work closely with experienced verification engineers to develop and maintain SystemVerilog - UVM test benches, assist in creating and integrating new verification components and debugging test cases. You'll receive hands-on training, tailored development plans, and support to enhance your technical expertise, strengthen your understanding of EDA tools, and progress toward more senior verification roles as your experience grows. This is a full-time role, Monday to Friday, 09:00AM - 17:00PM, with two days per week working from home.
This position would suit an aspiring Verification Engineer with foundational SystemVerilog and UVM knowledge, looking to join a global semiconductor leader that prioritises growth, professional development, and long-term career progression and the opportunity to boost earnings through a company bonus.
The Role:
Develop and maintain SystemVerilog - UVM test benches with full training and guidance
Support the design and integration of new verification components
Monday to Friday, 09:00AM - 17:00PM, with two days per week working from home
The Person:
Degree in Electrical/Electronic Engineering, Mathematics, Physics, Computing, or Robotics
Some experience or interest in SystemVerilog and UVM verification methods
Familiarity with EDA tools or scripting languages
Reference: BBBH21987
Keywords:
SVUVM, UVM, SV UVM, Specman-e, Functional Coverage, Testbench Development, Debugging, EDA Tools, Python, Scripting, IP Verification, Bristol, Hybrid
If you're interested in this role, click 'apply now' to forward an up-to-date copy of your CV.
We are an equal opportunities employer and welcome applications from all suitable candidates. The salary advertised is a guideline for this position. The offered renumeration will be dependent on the extent of your experience, qualifications, and skill set.
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