Position Summary
Complex SOC Top Physical Implementation for next-generation SoCs, involving synthesis, place and route, STA, timing, and physical signoffs.
Role and Responsibilities
* Hands-on experience in physical design and timing closure of complex blocks and full-chip designs.
* Strong understanding of timing, power, and area trade-offs and optimization of PPA.
* Proficiency with industry-standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and understanding their capabilities.
* Solid understanding of scripting languages such as Perl/Tcl and implementation flows.
* Experience with large SOC designs (>20M gates) with frequencies exceeding 1GHz.
* Expertise in block-level and full-chip SDC cleanup, synthesis optimization, low power checking, and logic equivalence checking.
* Familiarity with deep sub-micron designs (8nm/5nm) and related issues (manufacturability, power, signal integrity, scaling).
* Knowledge of typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed-signal block integration, and package interactions.
* Experience with hierarchical and top-down design, budgeting, timing, and physical convergence.
Skills and Qualifications
* Experience in top-level floorplanning, including partition shaping and sizing, pin placement, channel planning, high-speed signal and clock planning, and feed-through planning.
* Good understanding of Physical Design Verification methodologies to debug LVS/DRC issues at chip/block level.
* Participation in 4+ recent successful SoC tape-outs.
* 8 to 14 years of experience in physical implementation and design.
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