Job Description
1. Lead and mentor a team of analog engineers, including recruitment, training, and performance management.
2. Design and verify CMOS analog blocks for custom ASICs, meeting performance, area, power, and timescale constraints.
3. Drive full-chip projects from specification to production ramp, collaborating with analogue and digital leads on system and design strategy.
4. Oversee layout quality, produce high-quality documentation, and work with DFT engineers to ensure alignment with DFT strategy.
5. Manage silicon debugging, design characterisation, and support test development and production ramp.
6. Demonstrate expertise in analog circuit design through strong technical, communication, and organisational skills.
7. Drive continuous improvement in design methodologies, working practices, and team performance.
8. Take accountability for issue resolution, including silicon bugs, and proactively seek out and implement improvements.
9. Foster a positive team environment, ensuring timely delivery and first-time-right designs.
Key Performance Measures:
10. Team morale and performance, including on-time delivery and design quality
11. Progression and development of team members
12. Improvement in methodologies to reduce cost and time to tape-out
13. Demonstration of technical expertise, problem-solving capabilities, and innovative designs
14. Timely and accurate documentation and progress reporting
15. Continuous improvement of technical, non-technical, and management skills
Qualifications
16. Degree level qualification in Electronics/Microelectronics Engineering or a related discipline
17. 8+ years of relevant analogue circuit design experience
18. Extensive hands-on experience in designing and verifying various analogue circuit blocks (e.g., amplifiers, oscillators, LDOs, comparators, reference/biasing circuits, PMIC and audio sub-blocks)
19. Proven experience in managing a team of analogue engineers, including recruitment, performance management, and mentoring
20. Strong competence with EDA design tools, particularly the Cadence design environment
21. Experience in chip-level verification, including AMS and DMS
22. Ability to lead and deliver chip-level solutions through collaboration with cross-functional teams
23. Demonstrated skills in project management, including resource allocation and meeting tape-out milestones
24. Innovative problem-solving skills and ability to drive continuous improvement in design methodologies
25. Excellent verbal and written communication skills in English, with the ability to work effectively in a multi-site and multi-cultural environment
26. Flexibility to undertake occasional international travel