Senior Design Verification Engineer
Edinburgh
Join a world-class semiconductor powerhouse and play a key role in cutting-edge ASIC development.
I am looking for a Senior Design Verification Engineer to join a dynamic hardware development team in Edinburgh. In this role, you’ll be responsible for ensuring the functional correctness and robustness of complex digital and mixed-signal ASIC designs using advanced verification methodologies.
Key responsibilities
* Develop and execute comprehensive verification plans for complex mixed-signal ASIC designs
* Create and maintain UVM-based SystemVerilog testbenches.
* Write, debug, and execute test cases to verify functionality, performance, and corner cases
* Perform block-level and full-chip verification, including simulation, coverage analysis, and regression management
* Collaborate closely with design engineers to interpret specifications and define verification requirements
* Analyse and resolve issues discovered during verification and post-silicon validation
* Mentor junior engineers and drive improvements in verification methodologies and infrastructure
* Participate in code reviews and contribute to continuous improvement of design and verification best practices
Qualifications
* 5+ years’ experience in digital and/or mixed-signal design verification
* Strong proficiency in SystemVerilog, UVM, and leading simulation tools (e.g., Synopsys VCS, Cadence Xcelium)
* Solid understanding of digital design principles, RTL design, and ASIC development flows
* Experience with scripting languages (Python, Perl, Shell, etc.)
* Familiarity with formal verification, assertion-based verification, and coverage-driven verification techniques
* Excellent problem-solving skills and attention to detail
What’s on offer
* Competitive base salary plus RSUs and annual bonus
* A collaborative, innovative working environment
* Flexible work options – remote work may be considered for UK-based engineers with full right to work in the UK