The Opportunity
We are seeking a Digital Verification Engineer to join our Design Centre in Edinburgh, Scotland or Milan, Italy. Critical to Allegro's new product development plans, the Centre designs advanced power control IC's for a broad range of product applications. Allegro are recognised world-wide as providing state-of-the-art automotive power integrated circuits. You will be part of a new verification team which collaborates on the verification of gate-driver ICs and embedded SoCs based on innovative new core architectures.
What You’ll Do
* Developing comprehensive verification plans based on detailed microarchitecture specifications.
* Creating and maintaining SystemVerilog/UVM-based verification environments to achieve required coverage metrics.
* Defining and creating UVM-SV test environments, test plans, tests, and functional coverage.
* Analyzing test results, enhancing test coverage, and debugging unexpected design behavior.
* Running and maintaining regression test suites.
* Preparing and/or leading verification reviews.
* Collaborating with the System Engineering team on JAMA requirements.
* Identifying functional coverage conditions derived from microarchitecture specifications.
* Building mixed-signal testbenches, checkers, and tests.
* Implementing constrained random verification methodologies.
* Developing bus-functional models for verifying custom or industry-standard interfaces.
* Defining project deliverables and tasks, and tracking their on-time execution with a strong focus on quality.
Who You Are
* The successful candidate will possess at least a Bachelors degree in Electrical and/or Electronic Engineering or equivalent.
* Languages: System Verilog, Verilog, UVM/OVM, Specman, C/C++, ASM, TCL/TK, Python
* Knowledge of the embedded SoC design and verification life-cycle with an emphasis on design verification tasks such as: test plan development, test bench creation, test coverage analysis and debug of unexpected design behaviour.
* Knowledge of CPU, Memory or I/O Subsystem microarchitectures (caches, virtual memory, DMA, memory access optimizations).
* Experience identifying functional coverage conditions based on microarchitecture specifications
* Experience of SystemVerilog digital using UVM -SV
* Expertise building Mixed-Signal testbenches, checkers and tests.
* Expertise creating and using real-numbered analog behavioral models in SystemVerilog/Verilog-AMS or electrical behavioral models in Verilog-A
* Experience of script generation for processing results as well as regression control configuration
* Experience of constrained random verification.
* Experience of bus-functional model development for verification of custom or industry-standard interfaces.
* Experience defining team deliverables and tasks, tracking on time execution with a focus on quality.
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