An FPGA Design Engineer is needed to develop high-speed network interface cards. The key responsibilities include defining microarchitectures, implementing RTL, synthesising and timing-closing circuits, verifying and testing designs using SystemVerilog, and delivering and validating FPGA-based lab setups for trials.
Experience with FPGA tool flows (synthesis, partitioning, place and route, timing analysis) and a strong understanding of clock domain crossing techniques are crucial for this role. Excellent skills in SystemVerilog/Verilog/VHDL, scripting in Python/Tcl, and driver expertise are also required.
A good relevant degree and extensive hands-on industry experience of FPGA design for network applications at 100Gbps and above are necessary. You will have the chance to utilise your knowledge of PCIe, CXL, RDMA, DDR4, bare metal use of high-speed transceivers, Ethernet, IP, and other related technologies to drive innovation in the field of data centre technologies.