Arm Limited is looking for an experienced Verification Engineer to join their System IP team in Cambridge, UK. In this role, you will be responsible for the development of verification testbenches and improving existing methodologies. Ideal candidates should have at least 6 years of experience in verification design and formal properties verification techniques. Strong knowledge of System Verilog and experience with Cadence Jasper Gold tools are critical. Opportunities for mentoring and leading are available in this fast-paced environment.
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