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System-on-chip design engineer

Birmingham (West Midlands)
Digisourced.
Design engineer
Posted: 9 May
Offer description

Hello Network,



I hope you’re well,



We are currently working with HCL on a major Digital Transformation project for a large Semi-Conductor firm based across the UK/Europe. (Offices in Sophia Antipolis, France and in Cambridge, UK)



andidates should be able to travel to customer offices at a periodic cadence for f2f interactions.



We have multiple positions open, including the below primary role:



Common Information:


Customer: HCL for International Semi-Conductor Client

Duration: 15th May 2025 to 31st Aug 2026

Location: Remote in Sweden or UK

TRAVEL REIMBURSED BY CLIENT



Job Description:



* Micro-architecture development and reviews as needed, based on customer’s final requirement specification
* IP configuration management and rendering as per specification
* RTL coding and design reviews
* IP integration at SS/SOC level as defined by microarchitecture specification.
* Implement power intent using customer’s flow
* Trial synthesis and constraints updates, logical equivalency checking (LEC)
* Verification debug support



Required Skills & Knowledge:



* Micro-architecture design
* RTL coding in System Verilog
* Synthesis using Design Compiler/ Fusion compiler
* SDC development
* LEC failure debugs
* RTL / gate level debug experience using tools such as Verdi



There are also the below positions open: (please indicate which role you would prefer best):



Title: subsystem/SOC integration Senior Engineer

Experience: 5 to 10 years

No of positions: 3


Title: PCIE subsystem/SOC integration Lead Engineer

Experience: 10+ years

No of positions: 1

Note: For this position, candidate should have experience in integration of PCIE IP.


Title: PCIE subsystem/SOC integration Senior Engineer

Experience: 5 to 10 years

No of positions: 2

Note: For this position, candidate should have experience in integration of PCIE IP.


Title: DDR subsystem/SOC integration Senior Engineer

Experience: 5 to 10 years

No of positions: 1

Note: For this position, candidate should have experience in integration of DDR IP.


Title: EMMC_SDIO subsystem/SOC integration Lead Engineer

Experience: 10+ years

No of positions: 1

Note: For this position, candidate should have experience in integration of EMMC/ SDIO IP.



If you are interested, or you know someone that could be please reach out and we can arrange a time to speak?

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