Our client is a global technology leader developing next-generation processor architectures for flagship mobile, AI, and compute platforms.
Their CPU research and development team in Cambridge is expanding and is looking for an experienced Principal CPU Microarchitect to help shape future out-of-order CPU cores through advanced microarchitecture innovation, workload analysis, and performance modelling.
This is a highly technical architecture-focused role working closely with performance architects, compiler teams, runtime specialists, and downstream implementation teams on next-generation CPU technologies.
The Role
You will play a key role in defining and evaluating CPU microarchitectural features across modern out-of-order processor pipelines.
The position focuses heavily on cycle-accurate modelling, workload-driven optimisation, and architectural innovation targeting demanding mobile and compute workloads.
You will contribute across areas such as:
* Front-end architecture
* Memory subsystem optimisation
* Cache hierarchy and coherence
* Prefetching technologies
* ISA and semantic acceleration concepts
This is not an RTL or verification role. The focus is on architecture definition, performance modelling, and workload analysis.
Key Responsibilities
* Define and evaluate CPU microarchitectural features across multiple pipeline stages
* Develop and maintain cycle-accurate performance models using gem5 or similar simulators
* Analyse workloads using performance counters, traces, and profiling tools to identify bottlenecks and optimisation opportunities
* Evaluate architecture trade-offs for performance, power efficiency, and scalability
* Collaborate with compiler and runtime teams on ISA extensions and optimisation features
* Partner with implementation and design teams throughout feature development
* Produce detailed architecture specifications and technical documentation
* Mentor engineers and contribute to long-term CPU architecture strategy
Requirements
* MSc or PhD in Computer Science, Electrical Engineering, Computer Engineering, or related field
* Strong hands‑on experience in CPU microarchitecture
* Deep understanding of out-of-order processor design
* Expertise in one or more of the following:
* Prefetching
* Memory subsystem
* Cache coherence
* Experience with cycle-accurate simulators such as gem5
* Strong workload analysis and performance profiling experience
* Solid programming skills in C++ and Python
* Familiarity with ARM, x86, or RISC‑V architectures
Preferred Experience
* PhD in Computer Architecture or related field
* Publications in top architecture conferences such as ISCA, MICRO, HPCA, or ASPLOS
* Experience with dynamic language runtimes or compiler optimisation
* Exposure to AI/ML inference workloads on CPU platforms
* Experience contributing to production silicon
* Interest in AI-assisted architecture exploration and optimisation
#J-18808-Ljbffr