Join the team which delivers highly differentiated silicon into Blink and Ring battery powered devices. Our team works on state-of-the art SoCs in a vertically integrated team environment to deliver products our customers love. Drive early architectural and micro-architectural trade-offs to reduce time-to-revenue by shortening the time to revenue. Innovators will be delighted with our integrated verification/validation environment that is used to perform architectural modeling to post-silicon validation. The team works backwards from customer requirements to build super-low power, energy efficient designs that include the latest in AI, video processing, low power communications and CMOS fabrication technology.
Key job responsibilities
- Define architecture specifications based on requirements from product teams
- Create microarchitecture specifications suitable for being implemented by junior engineers
- Evaluate 3rd party IP blocks
- Estimate power, performance, and area for significant IPs early in design cycle
- Execute on design specifications to deliver high quality RTL
- Ensure quality by running and tracking results of front-end tools including: Synthesis, Lint (RTL, DFT, UPF), Power Analysis and STA
- Take the lead and work with verification teams to define functional coverage
- Work with pre-silicon verification teams to assist in defining testplans/testbenches
- Work with post-silicon validation teams to define and execute on testplans
- Write high quality documents to guide and lead a scalable team
BASIC QUALIFICATIONS
- Bachelor's degree in Electrical Engineering, Communications Engineering or related field, or equivalent experience
- Extensive experience in digital design
- Experience with products that have gone to volume production
- Hands on experience in low power design techniques
- Strong written and verbal skills
PREFERRED QUALIFICATIONS
- Master's or Ph.D degree in Electrical / Communications Engineering
- Extensive experience in digital design
- Exposure to Formal verification
- Experience with physical implementation flows