This role requires a mix of strategic engineering along with hands-on, technical work, being responsible for implementing complete chip design from netlist to tapeout, and having hands on experience in physical design and large chip integration. MSEE or equivalent is required. Deep experience with all aspects of ASIC integration including Floorplanning, Clock & Power distribution, global signal planning, I/O planning & hard IP integration. Knowledge of issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions. Familiar with hierarchical design approach, top-down design, budgeting, timing and physical convergence. Depth of expertise on integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain. Experience with large subsystem designs (>20M gates) with frequencies in excess of 1GHz applying brand-new technologies. Familiar with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt. From a CAD tool perspective, experience with Floorplanning tools, P&R flows, global timing verification and Physical Design Verification Flows is required.