Senior PDK & MMIC Layout Engineer
Purpose
To own and advance the design enablement infrastructure that underpins fabrication capability. This is a senior technical role sitting at the intersection of process engineering, MMIC design, and EDA tooling, responsible for the quality and integrity of Process Design Kits, mask artwork, and the design-to-fabrication flow across a portfolio of III-V technologies including GaAs, GaN, and InP.
Responsibilities
* Own the development, maintenance, and release of Process Design Kits (PDKs) across multiple compound semiconductor process nodes. This includes design rules, DRC/LVS decks, parameterised cells (PCells), technology files, and the PDK user handbook.
* Lead MMIC layout activities and mask procurement for both internal programmes and external foundry service customers, transforming customer designs into fully arrayed, fabrication-ready reticle designs to schedule and quality.
* Drive reticle designs in support of internal technology development, working in close collaboration with Process and Device Engineering to translate new process capabilities into validated design collateral.
* Chair and facilitate Design Reviews for the acceptance of new mask sets into the FAB, providing authoritative sign-off on layout correctness and design rule compliance.
* Own and evolve Process Control Monitor (PCM) designs in partnership with Device and Process Engineering, ensuring PCM coverage keeps pace with process development.
* Define and implement scripting and automation solutions in ADS and MWO to improve PDK deployment, layout efficiency, and reticle generation workflows.
* Serve as the primary technical interface for external customers using PDKs, and manage relationships with EDA vendors and mask suppliers.
* Act as the internal authority on design-to-fab flow, helping to raise capability and design quality across engineering teams, with scope to grow into a formal leadership or mentoring role as the team expands.
Skills & Experience
* Degree in Electrical Engineering, Physics, or a related STEM discipline; a postgraduate qualification is advantageous.
* Significant hands-on experience in MMIC layout and/or PDK development within a compound semiconductor environment (GaAs, GaN, or InP), typically 7+ years.
* Proficiency in ADS (Keysight) and/or MWO (AWR/Cadence) as primary layout and design tools.
* Strong scripting and programming capability — Python and/or SKILL/TCL — applied to PDK development, design rule automation, or layout tooling.
* Deep familiarity with DRC/LVS rule deck development and physical verification flows (Calibre or equivalent).
* Proven ability to work across the design-fabrication boundary, comfortable engaging with process engineers on design rule intent as well as with designers on layout implementation.
* Highly detail-oriented with a track record of owning technical documentation to a high standard.
* Strong communication skills; able to represent technical detail clearly to customers and internal stakeholders alike.
Apply or send a CV to imogen@waverecruitment.co.uk