Overview
Core scope: Design high-performance IP targeting FPGA/Adaptive SoC technology using SystemVerilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements.
Details
Work mode: Hybrid
Contract duration: 2 years
Location: Belfast
Role
Role Title: Senior IP Design Engineer
Core Scope
Design high-performance IP targeting FPGA/Adaptive SoC technology using SystemVerilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements.
Key Skills
* SystemVerilog RTL design
* 100Gb Ethernet, PCIe Gen5, AMBA/AXI
* Deep understanding of FPGA/Adaptive SoC design flow including P&R and timing closure
* Vivado/Vitis expertise
* Python/Tcl scripting
* Git & CI/CD experience
#J-18808-Ljbffr