We tackle the most complex problems in quantitative finance, by bringing scientific clarity to financial complexity. From our London HQ, we unite world-class researchers and engineers in an environment that values deep exploration and methodical execution - because the best ideas take time to evolve. Together we’re building a world-class platform to amplify our teams’ most powerful ideas. As part of our engineering team, you’ll shape the platforms and tools that drive high-impact research - designing systems that scale, accelerate discovery and support innovation across the firm. Take the next step in your career. The role Dates: 30 March 2026 – 18 September 2026 or 29 June 2025 – 18 September 2026 Working hours: 09:00–17:30 Location: Central London We’re looking for outstanding students to join us for a 12- or 24-week summer internship within our Research Technology function. As an FPGA Engineering Intern, you’ll work within a specialist team responsible for developing and optimising critical ultra-low latency systems on a global platform. This is a hands-on opportunity to apply your knowledge of digital design in a high-performance environment, solving real-world problems where nanoseconds matter. You’ll work at the interface of hardware and software, contributing to system design, testing and delivery. The role includes RTL development, simulation, and deployment, all with a focus on high reliability and speed. Key responsibilities of the role include: RTL development using SystemVerilog Writing automated testbenches for simulation and verification Contributing to continuous integration and delivery pipelines Developing supporting software in Python and C++ Collaborating with software engineers to integrate hardware solutions into production environments All of our interns receive a structured introduction to G-Research’s engineering and financial environment. You’ll be paired with a dedicated mentor who will support your technical and professional development during your time with us. You’ll also gain access to internal training, technical resources and the wider intern cohort network. Who are we looking for? We’re seeking capable, pragmatic engineers who are passionate about low-latency systems and digital design. You should be: Studying towards a 2:1 or above in Electrical Engineering, Computer Engineering, Computer Science or a related discipline Graduating in 2027 (penultimate-year students only) Confident writing RTL code in SystemVerilog, or a similar HDL Comfortable debugging, testing and analysing complex systems We value: Strong analytical skills and attention to detail Practical experience with scripting languages like Python or Perl Working knowledge of C++ Clear communication and an ability to collaborate across functions A proactive, hands-on mindset and a willingness to learn Previous experience in finance is not required. Why should you apply? This internship offers a unique opportunity to contribute to the design and optimisation of one of the most performance-sensitive parts of our global infrastructure. You’ll work alongside expert engineers, build production-grade systems and gain deep insight into how hardware can shape strategy in a competitive domain. Highly competitive compensation 30 days’ holiday pro rata 9% company pension contribution Opt-in private health insurance Informal dress code and excellent work/life balance Monthly company events Centrally located office (close to five stations and six tube lines) Interview process Online technical assessment Technical interviews Please note: due to the structure of our graduate hiring, we are only able to consider applications from those graduating in 2027. G-Research is committed to cultivating and preserving an inclusive work environment. We are an ideas-driven business and we place great value on diversity of experience and opinions. We want to ensure that applicants receive a recruitment experience that enables them to perform at their best. If you have a disability or special need that requires accommodation please let us know in the relevant section