Lead Debug/Trace/Profiling Design Engineer – SiFive, Cambridge, England, United Kingdom
SiFive is seeking a hardware design technical lead who is passionate about designing industry-leading debug, trace and profiling IP to help drive the tidal wave of adoption of RISC‑V as the architecture of choice for SOC designs across a broad variety of vertical applications.
Job Description
We build and maintain our RISC‑V processor subsystem IP using the Chisel hardware construction library embedded in the Scala language and are seeking a motivated individual to lead enhancement of our existing debug/trace/profiling hardware as well as development of new capabilities in this area. Opportunities exist to engage with customers, partners and tools vendors to help determine the future of the debug, trace and profiling solutions, as well as opportunities to engage with the RISC‑V International Association to help drive the state of the art of debug strategy.
Responsibilities
* Architect, design and implement debug, trace and profiling hardware.
* Work with architecture, performance, software and hardware teams in architecture/microarchitecture exploration and specification.
* Implement RTL generators such that elements self‑configure to optimally design‑in extensive configurability as a first‑class consideration.
* Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
* Perform initial sandbox verification, and work with design verification team to create and execute thorough verification test plans.
* Ensure that knowledge is shared via creation and maintenance of great documentation and participation in a culture of collaborative design.
Position Requirements
* Knowledgeable in debug, trace and profiling architecture and concepts.
* Knowledgeable in debug interfaces, JTAG, cJTAG.
* Knowledgeable in CPU architectures, power management and SoC design.
* Experience in debugging tools, profiling methods.
* Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL.
* Attention to detail and a focus on high‑quality design.
* Ability to work well with others and a belief that engineering is a team sport.
* Knowledge of at least one object‑oriented and/or functional programming language.
* Knowledge of one or more of: Chisel/Scala, RISC‑V architecture, Git/Jira/Confluence is a plus.
* 7+ years of industry experience leading and directly contributing to architecture, microarchitecture and RTL design for debug/trace/profiling hardware for high‑performance processors.
* MS/PhD in EE, CE, CS or a related technical discipline.
Pay & Benefits
Consistent with SiFive values and applicable law, we provide the following information to promote pay transparency and equity. Pay within these ranges varies and depends on job‑related knowledge, skills, and relevant work experience.
Base Pay Range
$193,500.00‑$236,500.00
In addition to base pay, this role may be eligible for variable/incentive compensation and/or equity. This role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!
Additional Information
This position requires a successful background and reference checks and satisfactory proof of your right to work in the United States of America. Any offer of employment for this position is also contingent on the Company verifying that you are authorized for access to export‑controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
As an E‑Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I‑9, Employment Eligibility Verification, upon hire. We do not use E‑Verify to pre‑screen job candidates and will comply with all E‑Verify regulations.
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