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Design verification engineer

West Town
G-Research
Verification engineer
Posted: 28 October
Offer description

G-Research is seeking a Design Verification Engineer to join our world-class Software Engineering function. As a Design Verification Engineer, you will provide technical expertise, support and guidance around formal verification tools. Working within our client's methodology and flows, you will oversee the effective application of formal verification. You will have excellent knowledge of industry standard interfaces and build tools, and be comfortable writing test plans, creating test benches and analysing code coverage.

We tackle the most complex problems in quantitative finance, by bringing scientific clarity to financial complexity. From our London HQ, we unite world-class researchers and engineers in an environment that values deep exploration and methodical execution — because the best ideas take time to evolve. Together we're building a world‑class platform to amplify our teams' most powerful ideas. As part of our engineering team, you'll shape the platforms and tools that drive high‑impact research — designing systems that scale, accelerate discovery and support innovation across the firm.


Responsibilities

* Develop System Verilog based VMM/UVM test bench environments
* Develop assertion based formal verification
* Develop co‑simulation environments to verify between C/C++ models and RTL modules
* Write test plans, create test bench specifications and analyse code coverage plans
* Implement constrained‑random sequences, agents and environments using the UVM methodology
* Develop and maintain complex verification environments using different methodologies, such as UVM and SV

We are looking for an engineer with extensive experience of large FPGA and ASIC design to join our Software Engineering function.


Qualifications

* Knowledge of industry‑standard interfaces, such as Avalon and AXI
* Experience with industry‑standard build tools, including version control
* Knowledge of QuestaSim environment
* Must have extensive experience with large FPGA/ASIC designs
* A background in fintech would also be beneficial

London, UK £65,563 per year - estimated. CLOSING SOON.


Benefits

* Highly competitive compensation plus annual discretionary bonus
* Lunch provided (via Just Eat for Business) and dedicated barista bar
* 35 days' annual leave
* 9% company pension contributions
* Informal dress code and excellent work/life balance
* Comprehensive healthcare and life assurance
* Cycle‑to‑work scheme
* Monthly company events


About G‑Research

G‑Research is committed to cultivating and preserving an inclusive work environment. We are an ideas‑driven business and we place great value on diversity of experience and opinions. We want to ensure that applicants receive a recruitment experience that enables them to perform at their best. If you have a disability or special need that requires accommodation please let us know in the relevant section.

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